1. Field of the Invention
The invention relates to a semiconductor memory cell, more particularly to an SRAM memory cell that consumes a relatively small amount of power when writing a write value of ‘0’ to the memory cell.
2. Description of the Related Art
Random access memories (RAM) can be classified into dynamic random access memories (DRAM) and static random access memories (SRAM), the latter being commonly employed in cache memories in view of their fast access times.
FIG. 1 illustrates a conventional SRAM memory cell that has a write port and a read port, and that is formed from eight transistors (T1-T8). The transistors (T1, T2) are PMOS field effect transistors, whereas the transistors (T3, T4) are NMOS field effect transistors. The transistors (T1, T3) are coupled in series to form a CMOS inverter 10. The transistors (T2, T4) are likewise coupled in series to form another CMOS inverter 20.
Each of the inverters 10, 20 is coupled between a power terminal (Vdd) and a ground terminal. The inverters 10, 20 are cross-coupled. That is, the transistors (T2, T4) of the inverter 20 have gate terminals that are coupled to a common connection node (D1) of the transistors (T1, T3) of the inverter 10, whereas the transistors (T1, T3) of the inverter 10 have gate terminals that are coupled to a common connection node (D2) of the transistors (T2, T4) of the inverter 20. The logic states at the nodes (D1, D2) indicate the logic state of the data bit stored in the memory cell.
The other transistors (T5-T8) of the memory cell act as access transistors. In particular, the transistors (T5, T6) are used for writing data, whereas the transistors (T7, T8) are used for reading data. Since state changes of these two transistor sets during read and write operations are analogous, only the activities of the transistors (T5, T6) during a write operation will be discussed in detail hereinafter.
Each of the transistors (T5, T6) is coupled to one of the nodes (D1, D2) at one end, and to a positive bit line (C1) or a negative bit line (C2) at another end. A word line (W) is coupled to the gate terminals of the transistors (T5, T6), and is responsible for controlling turn on and turn off activities of the transistors (T5, T6), thereby controlling writing of bit data through the positive or negative bit line (C1, C2).
In order to achieve fast access times, each of the bit lines (C1-C4) is pre-charged to a high logic state when there is no write or read activity. During a write operation, for example, when the write value is ‘1’, the positive bit line (C1) is maintained at the high logic state (i.e., Vdd), whereas the negative bit line (C2) is discharged to a low logic state. Accordingly, when the word line (w) is at the high logic state, the transistors (T5, T6) are turned on, thus turning off the transistor (T3) and turning on the transistor (T4). As a result, the node (D1) is at the high logic state, and the node (D2) is at the low logic state. This indicates that the data bit ‘1’ has been written to the memory cell. At the end of the write operation, the positive and negative bit lines (C1, C2) are once again pre-charged to the high logic state. In the same manner, when the write value is ‘0’, the positive bit line (C1) is at the low logic state, whereas the negative bit line (C2) is at the high logic state.
During a read operation, for example, when the read value is ‘1’, when the word line (R) is at the high logic state after pre-charging the positive and negative bit lines (C3, C4) to the high logic state, the transistors (T7, T8) are turned on. Since the transistor (T4) is also turned on and is grounded, the negative bit line (C4) will discharge via the transistor (T4), thereby resulting in a voltage difference between the positive and negative bit lines (C3, C4). Through the detection of a peripheral circuit (not shown), the data bit ‘1’ can be read accordingly.
During the write operation, regardless of whether the write value is ‘0’ or ‘1’, the logic state of one of the bit lines (C1, C2) is required to change from high to low (i.e., the logic states of the positive and negative bit lines must be opposite to each other). However, during pre-charging, the positive and negative bit lines (C1, C2) are both pulled to the high logic state. As a result, a substantial amount of power is wasted. This situation is evident when a current write value is different from that written beforehand, such as when a stored write value ‘0’ is to be overwritten by ‘1’, or when a stored write value ‘1’ is to be overwritten by ‘0’. In this instance, a full voltage swing occurs to ensure the required logic states at the nodes (D1, D2), which results in substantial power consumption.
In order to reduce power consumption, it has been proposed heretofore to use only half of the voltage swing amplitude when changing the bit line voltage. The proposed scheme, however, results in instability of the memory cell.
In U.S. Pat. No. 6,212,094, there is disclosed a low-power SRAM memory cell formed from five transistors and having one bit line and one word line for reading and writing data. Since there is only one bit line, power consumption is less than that of the conventional SRAM memory cell of FIG. 1. However, the asymmetric design of the proposed SRAM memory cell is directed to reducing power consumption when writing a write value ‘1’ to the memory cell.
In practice, upon examining instructions or data accessed from a cache memory, the number of ‘0’ bits is actually greater than the number of ‘1’ bits. In an actual test conducted using the SPEC2000 benchmarks, the proportion of ‘0’ bits to the total data can exceed 80%. Hence, there is a pressing need for an improved SRAM memory cell that can reduce power consumption when writing a write value of ‘0’.